
`timescale 1ns/1ns
module Bit_E_process
#(
	parameter	[10:0]	IMG_HDISP = 11'd1080,	
	parameter	[10:0]	IMG_VDISP = 11'd720
)
(
	
	input				clk,  				
	input				rst_n,				

	
	input				per_frame_v,	
	input				per_frame_h,		
	input				per_img_Bit,		
	
	
	output				post_frame_v,	
	output				post_frame_h,	
	output				post_img_Bit		
);


wire			matrix_frame_v;	
wire			matrix_frame_h;	
wire			matrix_p11, matrix_p12, matrix_p13;
wire			matrix_p21, matrix_p22, matrix_p23;
wire			matrix_p31, matrix_p32, matrix_p33;
Matrix_Generate_3X3_1Bit	
#(
	.IMG_HDISP	(IMG_HDISP),	
	.IMG_VDISP	(IMG_VDISP)
)
u_Matrix_Generate_3X3_1Bit
(
	
	.clk					(clk),  				
	.rst_n					(rst_n),				

	
	.per_frame_v		(per_frame_v),		
	.per_frame_h			(per_frame_h),		
	.per_img_Bit			(per_img_Bit),			

	
	.matrix_frame_v		(matrix_frame_v),	
	.matrix_frame_h		(matrix_frame_h),	
	.matrix_p11(matrix_p11),	.matrix_p12(matrix_p12), 	.matrix_p13(matrix_p13),	
	.matrix_p21(matrix_p21), 	.matrix_p22(matrix_p22), 	.matrix_p23(matrix_p23),
	.matrix_p31(matrix_p31), 	.matrix_p32(matrix_p32), 	.matrix_p33(matrix_p33)
);


//第一步
reg	post_img_Bit1,	post_img_Bit2,	post_img_Bit3;
always@(posedge clk or negedge rst_n)
begin
	if(!rst_n)
		begin
		post_img_Bit1 <= 1'b0;
		post_img_Bit2 <= 1'b0;
		post_img_Bit3 <= 1'b0;
		end
	else
		begin
		post_img_Bit1 <= matrix_p11 & matrix_p12 & matrix_p13;
		post_img_Bit2 <= matrix_p21 & matrix_p22 & matrix_p23;
		post_img_Bit3 <= matrix_p21 & matrix_p32 & matrix_p33;
		end
end

//第二步
reg	post_img_Bit4;
always@(posedge clk or negedge rst_n)
begin
	if(!rst_n)
		post_img_Bit4 <= 1'b0;
	else
		post_img_Bit4 <= post_img_Bit1 & post_img_Bit2 & post_img_Bit3;
end


reg	[1:0]	per_frame_v_r;
reg	[1:0]	per_frame_h_r;	
always@(posedge clk or negedge rst_n)
begin
	if(!rst_n)
		begin
		per_frame_v_r <= 0;
		per_frame_h_r <= 0;
		end
	else
		begin
		per_frame_v_r 	<= 	{per_frame_v_r[0], 	matrix_frame_v};
		per_frame_h_r 	<= 	{per_frame_h_r[0], 	matrix_frame_h};
		end
end
assign	post_frame_v 	= 	per_frame_v_r[1];
assign	post_frame_h 	= 	per_frame_h_r[1];
assign	post_img_Bit		=	post_frame_h ? post_img_Bit4 : 1'b0;

endmodule
